In 1971, Professor L.O. Chua first proposed The concept of Memristor in his paper "Memristor-The Missing Circuit Element" [1]. When studying the relationship between voltage, current, charge and magnetic flux, Professor Cai found that resistance, capacitance and inductance can all be represented by the relationship between voltage, current, charge and magnetic flux, as shown in Figure 1.1. In particular, resistance can be represented by the relationship between voltage and current, capacitance by the relationship between charge and voltage, and inductance by the relationship between current and magnetic flux. However, no one has yet proposed a device to represent the relationship between charge and magnetic flux. Cai calls it a memristor, which is expressed as dφ= MDQ.

Figure 1.1 The relationship of the four basic elements

In 2008, the scientific research team of HP Company successfully manufactured the first real memristor using TiO2 [2]. Figure 1.2 shows the schematic diagram of HP memristor, where D represents the width with TiO2 as the main body and W represents the width of the vacancy layer doped with oxygen. The resistance of both ends of the memristor will change with the change of current under the excitation of voltage.

Figure 1.2 HP memristor

Due to the relative lag of lithography technology and the doubling of the cost of shrinking wafer, semiconductor technology has approached quantum size, leading to the "post-molar" era of integrated circuit design. Currently, dynamic random access memory (DRAM) stores data in terms of the amount of charge in a capacitor, and the data is held for a short time. In order to maintain the data, it must be refreshed at regular intervals. If the storage cell is not refreshed, the stored information will be lost. In order to increase the retention time of data, capacitors must be designed large enough to reduce the refresh frequency, which will result in limited capacity and energy consumption and increase the process difficulty. And memory capacity is growing at a much slower rate than CPU performance. In addition, about half of the power consumption of the server comes from memory, and 40% of the power consumption of DRAM comes from refreshing, so as the capacity increases, the leakage power consumption will increase further. According to data from IDC, the global data volume has reached 41ZB in 2019, and the global data volume is maintaining a rapid growth. Increasingly large amount of data storage, including high-performance computing storage, and a variety of network applications will be more and more high requirements. Memristor is a kind of nanometer device with great development prospect. It has the advantages of high read-write speed, high integration density and low power consumption. Therefore, it will become a new star in the field of memory.

At present, the research of memristor in storage mainly shows in the following two aspects:

(1) The read-write control of a single memristor [3];

(2) Design and read-write optimization control of memristor array structure [3].

In 2013, Sandee Technology Company of the United States designed a 32 GB memristor memory chip using 1D1R structure and MEOX material [3-4]. The following year, Micron Technologies produced a 16 GB memristor memory chip using 1TIR structure and CUTE materials [3, 5]. At the same time, the memristor storage array can also be stacked in a three-dimensional structure [6-7], as shown in Figure 1.3.

Fig. 1.3 3D structure of memristor storage array

The physical realization of HP memristor and its application foreground have attracted people's attention, and various memristor models and simulators have been designed successively.

Currently, memristors and their simulators can be classified into the following four categories.

(1) Physical model [8-9] : Refers to physical devices with memristor properties produced from actual materials through certain processes. The HP memristor is the most typical example. At present, the material used to make memristor physical devices is usually oxide, such as titanium oxide, zinc oxide, etc.

(2) Mathematical model [10-11] : It refers to the model of constructing appropriate mathematical relations according to the characteristics of memristor and realizing the function of memristor with circuit components. Common mathematical models include piecewise linear model, quadratic nonlinear model and cubic nonlinear model.

(3) SPICE model [12-13] : refers to the model with memristor characteristics constructed by SPICE simulation software.

(4) Circuit Analog [14-15] : Refers to a model with memristor characteristics constructed from circuit elements. Since the physical components of memristors are not yet commercially available, and both the mathematical model and the SPICE model are only suitable for theoretical analysis, the circuitry simulation of memristors is very important. The circuit analog model of memristor is easy to be applied to the related hardware circuit experiments because it is constructed by circuit elements and has high research value.

reference

[1] Chua L O. Memristor-The missing circuit element. IEEE Transactions on Circuit Theory, 1971, 18(5): 507-519

[2] Strukov D B, Snider G S, Stewart D R, et al. The missing memristor found. Nature, 2008, 453(7191): 80-83

[3] Li Qingjiang, Liu Haijun, Xu Hui. Development Status and Future of Memristor. Defense Technology, 2016, 37(6): 9-16

[4] Liu T Y, Yan T H, Scheuerlein R, et al. A 130.7mm2, 2-Layer 32 Gb ReRAM memory device in 24 nm technology. IEEE Journal of Solid-State Circuits, 2013, 49(1): 140-153 

[5] Zahurak J, Miyata K, Fischer M, et al. Process integration of a 27nm, 16Gb Cu ReRAM. IEEE International of Electron Devices Meeting, San Francisco, CA, USA, 2014: IEDM14 (140-143)

[6] Xu X, Luo Q, Gong T, et al. Fully CMOS compatible 3D vertical RRAM with self-aligned self-selective cell enabling sub-5nm scaling., 2016 IEEE Symposium on VLSI Technology, Honolulu, HI, USA, 2016. 

[7] Chakrabarti B, Lastrasmontaño M A, Adam G, et al. A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit. Sci Rep, 2017, 7: 42429

[8] Ju H P, Dong S J, Kim T G. Improved uniformity in the switching characteristics of ZnO-based memristors using Ti sub-oxide layers. Journal of Physics D: Applied Physics, 2017, 50(1): 015104

[9] Sun Z, Wei L, Feng C, et al. Built-in-homojunction-dominated intrinsically rectifying-resistive switching in NiO nanodots for selection-device-free memory application. Advanced Electronic Materials, 2017, 3(1): 1600361

[10] Muthuswamy B. Implementing memristor based chaotic circuits. International Journal of Bifurcation and Chaos, 2010, 20(05): 1002651

[11] Li Q D, Zeng H Z, Li J. Hyperchaos in a 4D memristive circuit with infinitely many stable equilibria. Nonlinear Dynamics, 2015, 79(4): 2295-2308

[12] Yakopcic C, Hasan R, Taha T M, et al. Memristor-based neuron circuit and method for applying learning algorithm in Spice. Electronics Letters, 2014, 50(7): 492-494

[13] Xu K D, Zhang Y H, Yuan M Q, et al. Two memristor Spice models and their applications in microwave devices. IEEE Transactions on Nanotechnology, 2014, 13(3): 607-616

Liang Yan, Yu Dongsheng, Chen Hao. A Novel Memory Sensor Equivalent Model Based on Analog Circuit. Acta Physica Sinica, 2013, 62(15): 15850(1-10)

[15] Kim H, Sah M P, Yang C, et al. Memristor emulator for memristor circuit applications. IEEE Transactions on Circuits and Systems I: Regular Papers, 2012, 59(10): 2422-2431