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Brain-inspired computing based on emerging nonvolatile memory devices - Xin Zhang, PhD


Brain-inspired Computing based on Emerging Nonvolatile Memory Devices (1)

Artificial Intelligence (AI), which enables machines to think and act like humans, is undergoing a Renaissance, and it is not only a hot topic in academia today, but also has significant social implications (for example, the emergence of AlphaGo [1]). In recent years, artificial neural networks (i.e., machine/deep learning) have shown significantly improved accuracy in large-scale visual/auditory recognition and classification tasks, some of which even exceed the human level [2]. Figure 1 shows a basic deep neural network diagram, including an input layer, a hidden layer and an output layer. In particular, Convolutional Neural Network (CNN) [3] and Recurrent NN (RNN) [4] algorithms and their variants have proved their effectiveness in image, video, voice, and biomedical applications. FIG. 2 and FIG. 3 respectively show the schematic diagrams of CNN and RNN. To improve accuracy, the most advanced deep learning algorithms today tend to actively increase the depth and size of the neural network. For example, Microsoft's Res-Net (which won the ImageNet 2015 Image Classification Contest [5]) is over 100 layers deep [6]. This poses significant challenges to hardware implementations in terms of computing, memory, and communication resources. For example, Google's stacked auto-coding algorithm was able to successfully identify cat faces from 10 million random images taken from YouTube videos [7]. However, the task was done on a cluster of 16,000 processor cores, which consumed about 100 kilowatts of power and took three days to train the network.

Xin Zhang - Brain-inspired computing based on emerging non-volatile memory devices (I).png


Figure 1. Schematic diagram of deep neural network operation


FIG. 2 Schematic diagram of convolutional neural network operation


FIG. 3 Structure diagram of cyclic neural network (left) and its expansion form (right)

Today, deep learning is typically trained via a Graphic Processing Unit (GPU) accelerator in a data center or cloud platform. Specially designed accelerators such as SpiNNaker of Manchester [8] (FIG. 4), BrainScaleS of Heidelberger [9] (FIG. 5) and The Tensor Processing Unit of Google, TPU[10] has been developed to run large-scale neuromorphological and/or deep learning algorithms. In embedded systems or computing on the edge of the Internet of Things (IoT), such as autonomous driving, smart sensors, wearables, etc., there are serious design constraints in terms of performance, power, area, etc. In silicon complementary metal oxide semiconductor (CMOS) technology, IBM's TrueNorth[11], MITs Eyeriss[12] and a series of CNN accelerators [13]-[15] have developed application-specific integrated circuit (ASIC) on-chip solutions. However, there are still limitations in terms of on-chip memory capacity, off-chip memory access, and online learning capabilities. In particular, CMOS ASIC designs show that on-chip storage is the biggest bottleneck of energy efficiency computing, that is, storing millions of parameters and loading them from off-chip main memory to on-chip cache requires a large amount of energy and latency. Today's CMOS ASIC accelerators typically utilize static random access memory (SRAM) as the on-chip synaptic memory. Although SRAM technology has kept up well with CMOS scaling trends, the density of SRAM (100~200F2 per bit unit; Where F represents the technology node) and on-chip SRAM capacity (usually a few megabytes) are insufficient to store a large number of parameters (usually several hundred megabytes) in deep learning algorithms. The line-by-line operation of a traditional SRAM array limits the parallelism of the system, and leakage current is not desirable.

As an alternative hardware platform, emerging Nonvolatile Memory (eNVM) is proposed for on-chip weight storage with higher density (usually 4~12F2 per bit unit) and fast parallel simulation with low leakage power [16]. A special subset of eNVM devices that can display multistage resistance/conductance states can naturally simulate synaptic devices in neural networks, namely resistive synaptic devices [17]. Examples of Resistive synaptic devices include double-ended eNVMs, such as Phase Change Memory (PCM), Resistive Random Access Memory (RRAM), And a three-terminal ferroelectric transistor and a floating gate memory (with analog threshold voltage). The parallelism of the resistance cross bar array matrix vector multiplication (or dot product) further significantly accelerates the core neural computation (i.e., the weighted summation). A recent analysis by IBM showed that PCM based accelerators can train fully connected Multilayer Perceptron (MLP) at a lower power consumption than traditional Gpus [18]. By optimizing device technical parameters, it is possible that the ACCELERATOR based on eNVM is superior to the accelerator based on CMOS-ASIC SRAM synaptic array [19].

In the past few years, significant progress has been made in the research of enVM-based synaptic devices and their integration into the array level. At the device level, many candidates for resistive synaptic devices with tens to hundreds of conductance states have been demonstrated. Resistive synaptic devices can mimic biological synapses, where the migration/rearrangement of ions or atoms in solid media (e.g. oxides/chthiocompounds) can regulate the conductance between two electrodes, similar to how biological synapses regulate their conductance through the activation of volt-gated calcium channels. At the array level, there have been some experimental demonstrations of simple neural network algorithms using software and/or off-chip controllers from small scale (e.g. 12 × 12) to medium scale (e.g. 256 × 256). These demonstrations show great promise for future large-scale integration and prototyping of on-chip CMOS controllers. In addition, the development of computer-aided Design (CAD) or Electronic Design Automation (EDA) tools has facilitated the joint optimization of device performance with circuit/architecture and algorithm as the array size expands. To address design challenges related to device yield, device variability, and array parasitism. Groundbreaking simulation frameworks have been developed to evaluate the impact of device-level nonideality (finite weight accuracy, weight update nonlinearity/asymmetry, variation/noise, etc.) on the tradeoff between learning accuracy and training speed/energy.

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